Common operations by a processor in a computer system require identification of one or more sources of data to form an input to the processor as well as a destination for receiving the result of operating the processor. Conventional reduced instruction set computers (RISC devices) have used instructions all of a common bit length and format defining both the operation to be carried out by the processor as well as identification of two sources of data for use in the operation, and a destination for the result of the operation. Such instructions have been used to manipulate data that is found in addressable store locations such as registers or memory. When using a processor in a pipelined operation to execute a sequence of instructions it may be necessary to hold a plurality of live data items which are accessible by subsequent instructions. This requires sufficient number of addressable locations to be identified by an instruction that it either imposes a limit on the shortness of the instructions that can be used or a limit on the number of address locations that can be covered by an instruction set.
Other systems are known with complex instructions, (CISC devices) and such long instructions have provided the facility for identifying the addresses of more data stores used for holding live data during the pipelined processing of an instruction sequence. However such long instructions have required greater access time in obtaining the instructions from memory and may involve more extensive decoding needing more cycles of operation to achieve decoding of each instruction.
It is an object of the present invention to provide a computer system with instructions having a reduction in the number of address bits relative to the number of data items that may be held during instruction execution.